FUTURE ELECTRONIC DEVICES(beyond cmos)

"Beyond CMOS" refers to future technologies concerning digital logic, or future technologies, which is what we rely on to represent the sequences and signals within a digital circuit. These technologies are anticipated to stretch beyond the present CMOS scaling limits, which have already spanned over an order of magnitude in feature size and two orders of magnitude in speed

Complementary metal–oxide–semiconductor, abbreviated as CMOS, is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog    circuits    such     as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication.    In    1963, while    working for Fairchild Semiconductor, Frank Wanlass patented CMOS.

For the past forty years relentless focus on Moore’s Law transistor scaling has delivered ever-improving CMOS transistor performance and density. This presentation will discuss architectural and materials options that the research community has been investigating for the ultimate CMOS device. In addition, it will review emerging device options beyond the ultimate CMOS device including carbon-based, spin- based, tunnel-based and exciton-based devices that are being researched by universities. Now in this era of VLSI the technologies have been upgraded to a peak that the apple company has manufactured its A12 bionic chip with a unique design of ‘7nm’ technology.

 

 There are evolutionary and revolutionary advances that go beyond CMOS. The advances that retain the standard CMOS paradigm are evolutionary and the advances using novel devices that break out of the standard CMOS paradigm are revolutionary. Silicon material reached its limits while shrinking device dimensions. Besides MOSFET, the alternative technologies to overcome the short channel effects and performance improvements are Silicon on Insulator (SOI), Dual gate FETs, Carbon Nanotubes (CNTs), etc. The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a Complementary MOS  allows integrating more CMOS gates on an IC than in NMOS or bipolar technology.

In the near future, the eventual end to the roadmap of semiconductors is anticipated which hinders further scaling of CMOS technology. Alternative approaches are desired to satisfy those expectations to increase in the digital applications. The future of CMOS technology has got more innovative in examples like FinFet, Si-nanowire transistor, Junction less transistor, Single electron transistor. 

Now before going to advance semiconductors lets take overview of FET

The metal-oxide-semiconductor field-effect transistor is a type of field effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate; whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals.

                                                                     Fig.1 Construction of MOSFET

The basic principle of the field effect transistor was first patented by Julius Edgar Lilienfeld in 1925.The main advantage of a MOSFET is that it requires almost no input current to control the load current, when compared with bipolar transistors. In an enhancement mod MOSFET, voltage applied to the gate terminal increases the conductivity of the device. In depletion mode transistors, voltage applied at the gate reduces the conductivity.

The "metal" in the name MOSFET is now often a misnomer because the gate material is often a layer of polysilicon (polycrystalline silicon). Similarly, "oxide" in the name can also be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages. Since MOSFETs can be made with either p-type or n-type semiconductors, complementary pairs of MOS transistors can be used to make switching circuits with very low power consumption, in the form of CMOS logic.

 

CHALLENGES IN FABRICATION  TECHNOLOGY

§  Growing device and chip power dissipation.

§  Increasing process and device variability.

§  Degrade in device performance with scaling.

§  Formidable Lithography Capability and process complexities.

§  Degraded interconnect RC performance scaling.

§  Performance degradation in tight patch.

§  Electrical variations like Resistance.

§  Difficulties in mass production, it involves hundreds of process in fabrication.

§  N-well process for CMOS fabrication

§  P-well process

§  Twin tub-CMOS-fabrication process

Fig 2. CMOS Logic Gate using Pull-Up and Pull-Down 

      SOME ADVANCE DEVICES THAN CMOS

 

A. CNTFET

 

 Carbon nanotubes (CNTs) were discovered by Ijima in Japan in 1991. CNTs can be thought as rolled up sheets of distortion. Electrical properties depend on chirality or the direction of this distortion. CNTs can be metallic or semiconducting depending on the chirality. Basic principle operation of CNFET is the same as MOSFET where electrons are supplied by source terminal and drain terminal will collect these electrons. In other words, current is actually flowing from drain to source terminal. Gate terminal controls current intensity in the transistor channel and the transistor is in off state if no gate voltage is applied. Carbon nanotube field effect transistor (CNTFETs) uses semi conducting carbon nanotube as the channel, both p-channel and n-channel devices can be made from nanotubes. The physical structure of CNTFETs is very similar to that of MOSFETs and their I-V characteristics and transfer characteristics are also very promising and they suggest that CNTFETs have the potential to be a successful replacement of MOSFETs in nanoscale electronics. Of course, there are some distinct properties of CNTFETs, such as:

▪ The carbon nanotube is one-dimensional, which greatly reduces the scattering probability. As a result, the device may operate in ballistic regime.

▪ The nanotube conducts essentially on its surface where all the chemical bonds are saturated and stable. In other words, there are no dangling bonds which form interface states. Therefore, there is no need for careful passivation of the interface between the nanotube channel and the gate dielectric, i.e. there is no equivalent of the silicon/silicon dioxide interface.

▪ The Shot-key barrier at the metal-nanotube contact is the active switching element in an intrinsic nanotube device.

                                                                         Fig 3: Early CNTFET structure

 

 

Type of CNTFET-

The field effect transistors made of carbon nanotubes so far can be classified into:

• Back gate CNTFET
•  Top gate CNTFET  
• Wrap-around gate CNTFET
•   Suspended CNTFETs

 

1)      Back-gated CNTFET’s-

The earliest techniques for fabricating carbon nanotube (CNT) field-effect transistors involved pre-patterning parallel strips of metal across a silicon dioxide substrate, and then depositing the CNTs on top in a random pattern. The semiconducting CNTs that happened to fall across two metal strips meet all the requirements necessary for a rudimentary field-effect transistor. One metal strip is the “source” contact while the other is the “drain” contact. The silicon oxide substrate can be used as the gate oxide and adding a metal contact on the back makes the semiconducting CNT gateable.

Fig 4: Top and side view of carbon nanotubes deposited on a silicon oxide substrate pre-patterned with source and drain contacts

The types of back gate CNTFETs discussed so far have high contact resistances (≥1 MΩ), which led to a low transconductance gm (=dI/dVG) of about 10 -9A/V. This large contact resistance results from the weak van der Waals coupling of the devices to the noble metal electrodes in the ‘side-bonding’ configuration used. Here the SWNT is dispersed on top of the SiO2 film, and then source and drain electrodes made of transition metals compatible with silicon technology, such as Ti or Co, are fabricated on SWNT. Subsequent anneals at 400º C (Co) and, or at 820º C (Ti) in an inert ambient, form low resistance Co contacts or TiC contacts at the source and drain electrodes. Fig shows I-V characteristics of p-type CNTFET employing metallic Co or TiC contacts.

 

Top-gated CNTFET’s

 

Eventually, researchers migrated from the back-gate approach to a more advanced top-gate fabrication process [2]. In the first step, single-walled carbon nanotubes are solution deposited onto a silicon oxide substrate. Individual nanotubes are then located via atomic force microscope or scanning electron microscope. After an individual tube is isolated, source and drain contacts are defined and patterned using high resolution electron beam lithography. A high temperature anneal step reduces the contact resistance by improving adhesion between the contacts and CNT. A thin top-gate dielectric is then deposited on top of the nanotube, either via evaporation or atomic layer deposition. Finally, the top gate contact is deposited on the gate dielectric, completing the process.

 

Arrays of top-gated CNTFETs can be fabricated on the same wafer, since the gate contacts are electrically isolated from each other, unlike in the back-gated case. Also, due to the thinness of the gate dielectric, a larger electric field can be generated with respect to the nanotube using a lower gate voltage. These advantages mean top-gated devices are generally preferred over back-gated CNTFETs, despite their more complex fabrication process.

                                               Fig 5: Structure of Top gated CNTFET

 

 Wrap-around gate CNTFET’s

Wrap-around gate CNTFETs, also known as gate-all-around CNTFETs were developed in 2008 [3],and are a further improvement upon the top-gate device geometry. In this device, instead of gating just the part of the CNT that is closer to the metal gate contact, the entire circumference of the nanotube is gated. This should ideally improve the electrical performance of the CNTFET, reducing leakage current and improving the device on/off

                                                                                               Fig 6: Sheathed cnt

Device fabrication begins by first wrapping CNTs in a gate dielectric and gate contact via atomic layer deposition. These wrapped nanotubes are then solution-deposited on an insulating substrate, where the wrappings are partially etched off, exposing the ends of the nanotube. The source, drain, and gate contacts are then deposited onto the CNT ends and the metallic outer gate wrapping.

 

Suspended CNTFET’s

 

CNTFET device geometry involves suspending the nanotube over a trench to reduce contact with the substrate and gate oxide [5]. This technique has the advantage of reduced scattering at the CNT-substrate interface, improving device performance [5] [6] [7]. There are many methods used to fabricate suspended CNTFETs, ranging from growing them over trenches using catalyst particles [5], transferring them onto a substrate and then under-etching the dielectric beneath [7], and transfer-printing onto a trenched substrate [6]. 

 

                                                                                       Fig 7: Suspended CNTFET device

 

The main problem suffered by suspended CNTFETs is that they have very limited material options for use as a gate dielectric (generally air or vacuum), and applying a gate bias has the effect of pulling the nanotube closer to the gate, which places an upper limit on how much the nanotube can be gated. This technique will also only work for shorter nanotubes, as longer tubes will flex in the middle and droop towards the gate, possibly making touching the metal contact and shorting the device. In general, suspended CNTFETs are not practical for commercial applications, but they can be useful for studying the intrinsic properties of clean nanotubes.

B. FINFET

      FinFET, also known as Fin Field Effect Transistor, is a   type   of   non-planar   or   "3D" transistor used   in   the   design    of   modern processors. As in earlier, planar designs, it is built on an SOI (silicon on insulator) substrate.

                                                             Fig 8. FINFET Construction

However, FinFET designs also use a conducting channel that rises above the level of the insulator which is called a gate electrode. This fin-shaped electrode allows multiple gates to operate on a single transistor. This type of multi-gate process extends Moore's law, allowing semiconductor manufacturers to create CPUs and memory modules that are smaller, perform faster, and consume  less energy. Intel began     releasing FinFET CPU technology in 2012 with its 22- nm Ivy Bridge processors.

FinFET technology has been born as a result of the relentless increase in the levels of integration. The basic tenet of Moore's law has held true for many years from the earliest years of integrated circuit technology. Essentially it states that the number of transistors on a given area of silicon doubles every two years. Some of the landmark chips of the relatively early integrated circuit era had a low transistor count even though they were advanced for the time. The 6800 microprocessors for example had just 5000 transistors. Todays have many orders of magnitude more. To achieve the large increases in levels of integration, many parameters have changed. Fundamentally the feature sizes have reduced to enable more devices to be fabricated within a given area. However other figures such as power dissipation, and line voltage have reduced along with increased frequency performance.

C. Gate all around FET

     A gate all around (GAA) FET, also known as a surrounding-gate transistor is similar in concept to a FinFET except that the gate material surrounds the channel region on all sides. Depending on design, gate all around FETs can have two or four effective gates. Gate all around FETs have been successfully characterized both theoretically and experimentally. They have also been successfully etched onto InGaAs nanowires, which have a higher electron mobility than silicon. GAAFET are the successor to FinFETs as they can work at sizes below 7nm. They were used by IBM to demonstrate 5 nm process technology.

         A gate all around MOSFET was first demonstrate in1988, by a Toshiba research team including Fujio Masuoka , Hiroshi Takato and Kazumasa Sunouchi, who demonstrated a vertical nanowire GAAFET which they can called a "surrounding gate transistor"As of 2020, Samsung and Intel have announced plans to mass produce GAAFET transistors while TSMC has announced that they will continue to use FinFETs in their 3nm node, dissipate TSMC developing GAAFET transistors.

                                                                     Fig9: Gate all around FET

D.SI-NANOWIRE TRANSISTOR

   All modern transistors have a gate electrode, which controls the flow of holes and electrons between the source and drain contacts. In CMOS transistors, this modulation relies on the presence of a junction between the channel and the source and drain contacts. With the decreasing dimensions of modern transistors, generating these junctions is becoming increasingly difficult. The first patented field effect transistor, suggested by Julius Edgar Lilienfeld, in the 1920's was a junction-free device. The device was designed such that charge carriers could be depleted by the actions of the gate. However, in order to be able to fully turn off the device, a very thin nanoscale channel (nanowire) is required. The technology

                                                  Fig 10. SI NANOWIRE Transistor Construction

for generating such thin structures did not exiunction less transistor was manufactured in 2010 by Colinge et al. Using standard Silicon on Insulator (SOI) technology and electron-beam lithography, they were able to produce the first junction less transistor

The light blue (bottom) surface depicts the bottom of the wafer, such that the volume between the two blue surfaces is the silicon wafer. The first step is the generation of the oxide mask layer shown in Figure, followed by the application of the silicon nanowire using an AFM in NCM in Figure. Subsequently, TetraMethylAmmonium Hydroxide (TMAH) is used in order to selectively and anisotropically etch away the silicon. TMAH is etching process which has an approximate 1:1000 etch ratio for SiO2 with respect to silicon. The final step is the removal of the silicon dioxide, which is done once again using wet etching, but with hydrofluoric acid (HF).

E. SINGLE ELECTRON TRANSISTOR

  A single-electron transistor (SET) is a switching device that consists of two tunnel junctions sharing a common electrode and makes use of this controlled electron tunneling for amplification of current. The technology used in single-electron transistors is based on the theory of quantum tunneling. Considered an important component of nanotechnology, single-electron transistors provide high operating speed and low power consumption.A single-electron transistor is usually made by keeping two tunnel junctions in series. The transistor consists of a source electrode and a source drain, which is joined with the help of a tunneling island that is also capacitively connected to a gate. The electrons can travel to another electrode only through the insulator. The resistance feature of a single-electron transistor depends on the size of the nanoparticles, capacitance ad electron tunneling. Single-electron transistors have many applications. They can be used as ultrasensitive microwave detectors and can also be used to detect infrared signals at room temperature. They are also efficient charge sensors capable of reading spin or charge qubits. Their high sensitivity feature allows them to be used as electrometers in experiments requiring high levels of specificity.

Fig 11. Single Electron Transistor

 

FUTURESCOPE

      Present work is fare enough to study the performance analysis of Hybrid SET-CMOS based logic circuits; still there are some suggestions for future work which can enhance the accuracy of the present work. Future scope of CMOS includes for the scaling down to 10 NM. The optimization of the CMOS will play a crucial role in the development.

NanoCMOS will likely continue to supply the world with intelligent devices for a long time and grow to be a much larger industry. NanoCMOS will be platform for deploying innovations in materials, devices, circuits and nanotechnologies for electronic and other application. The performance of integrated circuits has been improving exponentially for more than thirty year. during the next decade, the industry must overcome several technological challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit designs are outlined. possible solutions are briefly discussed. the ways in which these challenges will affect future growth in the industry are considered.

The future of CMOS technology got more innovative in examples like FinFet, Si- nanowire transistor, Junction less transistor, Single electron transistor

 

                     APPLICATIONS

         CMOS IMAGE SENSOR-

     CMOS (complementary metal-oxide- semiconductor) cameras are a type of image captures device that utilize an image sensor to register visible light as an electronic signal. These types of cameras do not use photochemical film to capture stills or video. Instead, the electronic signal is recorded to either an internal memory or a remotely connected device. CMOS technology was rather immature until recently, and CMOS image sensors are increasing in popularity. CMOS imaging systems are—as a whole—simpler, despite the complex development of CMOS image sensors themselves. CMOS sensors are somewhat more responsive than CCD, and have a higher imaging speed. The pixel readout on CMOS sensors allows for window-of-interest readouts, useful for image   

 Fig11 : CMOS IMAGE SENSOR

 

 compression, motion detecting, and target tracking. CMOS image sensors also require significantly less power. CMOS image sensors can produce comparable-quality images, with almost no blooming effect.

§  In microcontrollers

§  In static ram

§  In data converter

§  In integrated trans receivers.

 

 

     REFERENCE

[1] https://www.ieee.exploree/cmos/researchpaper

[2] Kevin f. brennan , introduction to semiconductor devices and device beyond cmos technology , Cambridge publication , 2016

[3] F. Ellinger, m. claus, m. schroter and c. carta, review of advanced and beyond cmos fet technologies for radio frequency circuit and nanotechnology applications, published microwave and optoelectronics conference (IMOC) 2011 SBMO.

[4] ITRS – international technology roadmap for CMOS ,2013

[5] INTEL semiconductor and nanotechnology review by DR. saurabh batti. In research all the applications beyond cmos technology.

[6] https://www.ieee.exploree/cmos/researchpaper

[7] D.e. nikonov, G.I. bourianoff, and P.A. gargini “simulation of highly advanced devices beyond CMOS” vol.33, 2017

[8] https://en.wikipedia.org/wiki/devicebeyondCMOS

[9] https://www.ieee.exploree/technologyadvancesbeyondcmos

[10] Bao Liu, Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture, Published in Design Automation Conference, IEEE, 2009.

 

 

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