SI-NANOWIRE TRANSISTOR

   All modern transistors have a gate electrode, which controls the flow of holes and electrons between the source and drain contacts. In CMOS transistors, this modulation relies on the presence of a junction between the channel and the source and drain contacts. With the decreasing dimensions of modern transistors, generating these junctions is becoming increasingly difficult. The first patented field effect transistor, suggested by Julius Edgar Lilienfeld, in the 1920's was a junction-free device. The device was designed such that charge carriers could be depleted by the actions of the gate. However, in order to be able to fully turn off the device, a very thin nanoscale channel (nanowire) is required.

 

 The technology for generating for generating such thin structures did not exiunction less transistor was manufactured in 2010 by Colinge et al. Using standard Silicon on Insulator (SOI) technology and electron-beam lithography, they were able to produce the first junction less transistor

The light blue (bottom) surface depicts the bottom of the wafer, such that the volume between the two blue surfaces is the silicon wafer. The first step is the generation of the oxide mask layer shown in Figure, followed by the application of the silicon nanowire using an AFM in NCM in Figure. Subsequently, TetraMethylAmmonium Hydroxide (TMAH) is used in order to selectively and anisotropically etch away the silicon. TMAH is etching process which has an approximate 1:1000 etch ratio for SiO2 with respect to silicon. The final step is the removal of the silicon dioxide, which is done once again using wet etching, but with hydrofluoric acid (HF).

article by 

AMRUTA LHAYAKAR